1. Field of the Invention.
This invention is directed to electronic systems for providing stable clock signals, in general, and to a system which provides stable clock signals with low jitter and low slew rate by using isochronous conversion techniques, in particular.
2. Prior Art.
There are many uses of multiplexing systems in the art. Many of these multiplexing systems require and/or provide an interface with data sources and data utilization devices which are not quite synchronized to the multiplexer. These data sources and utilization devices must then be synchronized in a separate operation. The technique of synchronizing a number of "near synchronous inputs" is known as "isochronous conversion."
In performing the multiplexing operations, the various input sources provide signals at specified data rates. The data rate which can be transferred through any multiplexer channel is limited to an integer multiple of the channel rate. As a consequence, differences between the data rate and the channel rate are not unusual. To permit system compatibility, any difference in the number of signals from the integer multiple is provided in the form of special data bits which are referred to as "filler data bits".
In particular, the filler data bits are a group of bits which are transferred in the multiplex format and which are reserved (or stored) to be periodically transmitted as the extra, accumulated bits of the isochronous channel. However, these filler data bits must be identified in the system so that the system will know whether to respond to filler data bits which contain real data or to ignore filler bits which contain no meaningful data. Consequently, control bits are usually transmitted as part of the signals so that the frame in which the filler data bits are stored can be properly identified.
Another aspect which must be considered is that the filler data bits are supplied in particular frames of the multiplexer operation but not in every frame of this operation. Thus, a number of data bits or information signals will be transmitted as a burst of information on the multiplexer channel. It is highly desirable to attempt to make this data transmission as smooth as possible so that the isochronous data channel appears essentially transparent to the user. In a typical configuration known in the prior art, the isochronous data channel includes a multiplexer (MUX) and a demultiplexer (DEMUX). Storage registers (FIFO) are associated with the input of the MUX and the output of the DEMUX. The FIFO registers produce control signals in the transmission channel in response to the application of signals thereto. The significant apparatus for controlling the transmission quality is usually in the DEMUX circuit portion. Typically, the bursts of data from the DEMUX are fed to the associated FIFO. This FIFO acts as a buffer to absorb the data bursts and provide a smooth data output by the clock provided by the clock generator. That is, the clock output signals of the clock generator should be identical to the clock input signals supplied to the MUX FIFO in both symmetry and jitter. This condition avoids degradation of the user data transfer and also allows proper interfacing with other transmission devices, e.g. modems and the like.
In the past, attempts were made to distribute the multiplexed and filler data bit locations equally within a frame. This was done to more equally separate the data bits fed to the DEMUX FIFO. However, even with this smoothing, the clock generators utilized in the prior art produced clock signals which have unacceptably slow rates, high jitter and other shortcomings.
Because of these undesirable characteristics, it has been difficult for the prior art systems to achieve a totally synchronous, locked-in operation. Moreover, these prior art systems were unstable inasmuch as they would continually sweep or hunt on or about the nominal isochronous frequency. This hunting gave an oscillatory, unstable aspect to the operation of the prior art systems. Consequently, new and improved systems of this type are highly desirable.